[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default

[Maximilian Brune (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier.

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email )

Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
......................................................................

soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default

TODO justification

Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062
Signed-off-by: Maximilian Brune 
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/soc/amd/cezanne/chipset.cb
2 files changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/86272/1

diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index b58dc2c..1f1b000 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -350,6 +350,8 @@
    			end
    		end # Audio
    	end
+		device ref gpp_bridge_b on  # Internal GPP Bridge 1 to Bus B
+		device ref gpp_bridge_c on  # Internal GPP Bridge 2 to Bus C

device ref lpc_bridge on
    		chip ec/google/chromeec
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index ccce485..14dba64 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -22,7 +22,7 @@
    	device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end

device pci 08.0 on end # Dummy device function, do not disable
-		device pci 08.1 alias gpp_bridge_a off  # Internal GPP Bridge 0 to Bus A
+		device pci 08.1 alias gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		ops amd_internal_pcie_gpp_ops
    		device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
    		device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
@@ -83,14 +83,14 @@
    		device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
    		device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
    	end
-		device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+		device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B
    		ops amd_internal_pcie_gpp_ops
    		device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
    		device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
    		device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
    		device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
    	end
-		device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+		device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
    		ops amd_internal_pcie_gpp_ops
    		device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
    		device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio