12 Nov
2021
12 Nov
'21
1:57 a.m.
Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )
Change subject: soc/intel/alderlake: Disable VT-d for early silicons ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/59191/comment/e7eb7327_c6de8c8a PS3, Line 264: cpu_get_cpuid() == CPUID_ALDERLAKE_A0 || CPUID_ALDERLAKE_A1
Ooph my eyes are broken today, thanks Felix 😄 […]
Looks good to me 😊
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
Gerrit-Change-Number: 59191
Gerrit-PatchSet: 3
Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Reviewer: Abhijeet Rao abhijeet.rao@intel.corp-partner.google.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Felix Singer felixsinger@posteo.net
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