[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37319

to look at the new patch set (#9).

Change subject: soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
......................................................................

soc/intel/cannonlake: Configure GPIO PM configuration in bootblock

This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.

BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb

Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/chip.c
A src/soc/intel/cannonlake/gpio_common.c
M src/soc/intel/cannonlake/include/soc/gpio.h
5 files changed, 53 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37319/9