[coreboot-gerrit] Change in coreboot[master]: cpu/x86/entry16: Do not disable cache when Boot Guard is supported

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38252 )

Change subject: cpu/x86/entry16: Do not disable cache when Boot Guard is supported
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38252/7/src/cpu/x86/16bit/entry16.i... 
File src/cpu/x86/16bit/entry16.inc:

https://review.coreboot.org/c/coreboot/+/38252/7/src/cpu/x86/16bit/entry16.i... 
PS7, Line 120: #if CONFIG(INTEL_BOOTGUARD)
Just my personal preference, there is a read-modify-write sequence on cr0 that I would rather not see split to so many lines. Specially with rdmsr there in the middle register usage is not so obvious.

#if CONFIG(INTEL_BOOTGUARD)
    /* DO NOT disable cache if Intel BootGuard is supported */
    movl	$BOOTGUARD_SACM_INFO, %ecx
    rdmsr
    test	$1, %eax
    jz	1f
    movl	%cr0, %eax
    andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
    orl	$0x01, %eax /* PE = 1 */
    movl	%eax, %cr0
    jmp	2f
#endif
1:
    movl	%cr0, %eax
    andl	$0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
    orl	$0x60000001, %eax /* CD, NW, PE = 1 */
    movl	%eax, %cr0
2: