[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Update microcode before FSP

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36198 )

Change subject: soc/intel/braswell: Update microcode before FSP
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Patch Set 3:
> Patch Set 3:
> > Any boot time penalty?
>
> on google/cyan, it's actually 50ms faster than the previous working build (pre-C_ENVIRONMENT_BOOTBLOCK)

Previously ROM caching was only set up after microcode update while here it is done before. That probably explains the speedup. BTW FSP does not set up caching before microcode updates either so this patch series likely improves bootspeed in general.