[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: configure L1Substate for PCIe

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39413 )

Change subject: mb/google/volteer: configure L1Substate for PCIe
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mb/google/volteer: configure L1Substate for PCIe

Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.

Reference: #613582 Tiger Lake PCH-LP Sightings Report
           issue id #1409566330

BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe

Signed-off-by: Wonkyu Kim 
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) 
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Nick Vaccaro 
---
M src/mainboard/google/volteer/variants/ripto/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/volteer/variants/ripto/overridetree.cb b/src/mainboard/google/volteer/variants/ripto/overridetree.cb
index 32204c5..162f93b 100644
--- a/src/mainboard/google/volteer/variants/ripto/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/ripto/overridetree.cb
@@ -1,5 +1,10 @@
 chip soc/intel/tigerlake

+	# NVMe warm reboot workaround
+	# Limit L1.1 (value:2) for RP9, RP11
+	register "PcieRpL1Substates[8]" = "2"
+	register "PcieRpL1Substates[10]" = "2"
+
    device domain 0 on
    end