[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Kane Chen.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 2:

(3 comments)

Patchset:

PS2:
> I believe we need to default disable USB2 PHY power gating for all ADL-P devices irrespective of int […]

@subrata, as per Intel doc#723158, when extern VR is used, then reported issue may not occur. So, I expect developer should enable the UPD if USB2 phy power gating  to be disabled.

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/585baf45_1b453fdb 
PS2, Line 572: orderto
> order to

Ack

https://review.coreboot.org/c/coreboot/+/63293/comment/de69f197_f38775c7 
PS2, Line 572:
> One space.

Ack