[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/acpi: Fix hang caused by IVRS

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45056 )

Change subject: soc/amd/picasso/acpi: Fix hang caused by IVRS
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Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45056/2/src/soc/amd/picasso/acpi.c 
File src/soc/amd/picasso/acpi.c:

https://review.coreboot.org/c/coreboot/+/45056/2/src/soc/amd/picasso/acpi.c@... 
PS2, Line 55: 0 - max logical cpus - 1
This reads as 0 - max logical cpus. i.e., a negative number. Maybe better written as [0, max logical cpus - 1], or maybe [0, max logical cpus)

https://review.coreboot.org/c/coreboot/+/45056/2/src/soc/amd/picasso/acpi.c@... 
PS2, Line 64: nb_ioapic_base
If this is zero can we skip writing the nb ioapic? This way we don't write an invalid value if FSP is out of date.