Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 )
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ......................................................................
Patch Set 39:
(3 comments)
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig File src/soc/intel/broadwell/Kconfig:
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig@117 PS37, Line 117: default 0x2000
Tested?
I think the linker tells you if that is not enough?
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/c... File src/soc/intel/broadwell/bootblock/cpu.c:
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/c... PS37, Line 51:
Was this redundant with `non-evic/cache_as_ram. […]
The only reason this was done, was to speed up finding the microcode updates. cache_as_ram.S cleared it anyway. Now cache_as_ram.S updates the microcode itself (also after caching the rom to speed up things)
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/ro... File src/soc/intel/broadwell/romstage/romstage.c:
https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/ro... PS37, Line 68: struct romstage_params rp = { : .bist = 0, /* checking done in the bootblock */ : .pei_data = NULL, : };
If I read this correctly, we are effectively passing […]
At the moment we try to have the same romstage interface with or without romcc bootblock (which passes on BIST) for all cpu/intel/car/ users. I'll clean it up when that is done for all platforms. OTOH it looks like broadwell has everything in soc/intel/broadwell so a cleanup now, seems like a good idea.