Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17661
-gerrit
commit fd41c3d79a1bba639e0f6729476b293fff34c157 Author: Arthur Heymans arthur@aheymans.xyz Date: Wed Nov 30 20:37:29 2016 +0100
nb/x4x: Move checkreset before SPD reading
It makes no sense to read SPDs if the system will reset anyway.
Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/northbridge/intel/x4x/raminit.c | 37 +++++++++++++++++++++++++++++++ src/northbridge/intel/x4x/raminit_ddr2.c | 38 -------------------------------- 2 files changed, 37 insertions(+), 38 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 86f63f1..aaf1cee 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -314,6 +314,41 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } }
+static void checkreset_ddr2(struct sysinfo *s) +{ + u8 pmcon2; + u32 pmsts; + + if (s->boot_path >= 1) { + pmsts = MCHBAR32(PMSTS_MCHBAR); + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } + + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + + printk(BIOS_DEBUG, "Reset...\n"); + outb(0x6, 0xcf9); + asm ("hlt"); + } + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); +} + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -326,6 +361,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff);
+ checkreset_ddr2(&s); + memset(&s, 0, sizeof(struct sysinfo));
s.boot_path = boot_path; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9c414e2..587851c 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -259,41 +259,6 @@ static void clkcross_ddr2(struct sysinfo *s) MCHBAR32(0x70c) = clkxtab[i][j][12]; }
-static void checkreset_ddr2(struct sysinfo *s) -{ - u8 pmcon2; - u32 pmsts; - - if (s->boot_path >= 1) { - pmsts = MCHBAR32(PMSTS_MCHBAR); - if (!(pmsts & 1)) - printk(BIOS_DEBUG, - "Channel 0 possibly not in self refresh\n"); - if (!(pmsts & 2)) - printk(BIOS_DEBUG, - "Channel 1 possibly not in self refresh\n"); - } - - pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - - if (pmcon2 & 0x80) { - pmcon2 &= ~0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - - /* do magic 0xf0 thing. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - - printk(BIOS_DEBUG, "Reset...\n"); - outb(0x6, 0xcf9); - asm ("hlt"); - } - pmcon2 |= 0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); -} - static void setioclk_ddr2(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; @@ -1947,9 +1912,6 @@ void raminit_ddr2(struct sysinfo *s) // Select timings based on SPD info sdram_detect_smallest_params2(s);
- // Reset if required - checkreset_ddr2(s); - if (s->boot_path != BOOT_PATH_WARM_RESET) { // Clear self refresh MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR)