[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Cascade Lake SP support

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35126

to look at the new patch set (#4).

Change subject: soc/intel: Add Cascade Lake SP support
......................................................................

soc/intel: Add Cascade Lake SP support

Adds Xeon Cascade Lake processor CPUIDs and SkyLake-E Host Bridge
PCI Id

Change-Id: If351d554db62c51849ff6c7bb49074e587f14e6d
Signed-off-by: Maxim Polyakov 
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/skylake/bootblock/report_platform.c
5 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35126/4