[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email )

Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS
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Patch Set 4:

(2 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/86002/comment/0a9f4429_7db16ffd?usp... :
PS4, Line 19: 	select FSP_DEBUG_LOG_LEVEL_USING_CBFS if MAINBOARD_HAS_CHROMEOS
> Why does it depend on MAINBOARD_HAS_CHROMEOS?

There is a dependency that allows us to stitch debug FSP into AP FW image. However, not all PTL platforms stitch debug FSP into AP FW. Therefore, some special steps exist in our cros ebuild that allow us to handle the soc firmware log level dynamically. These steps may not be flexible for other platforms, and we shouldn't assume that every PTL design will bake debug FSP binary into their AP FW.

File src/soc/intel/pantherlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/86002/comment/0d204df8_408147cc?usp... :
PS4, Line 314: 	if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS) && is_enabled) {
> It looks quite a cumbersome construction to me, what adding and using the following helper function:
> static enum fsp_log_level fsp_get_log_level(bool is_enabled)
> {
>    if (!is_enabled)
>    	return FSP_LOG_LEVEL_DISABLE;
>
>    if (CONFIG(FSP_DEBUG_LOG_LEVEL_USING_CBFS))
>    	return get_fsp_mrc_debug_log_level();
>
>    return fsp_map_console_log_level();
> }

There are two log levels for handling general FSP and MRC serial output, and each can be handled separately during boot. Therefore, we are calling into get_fsp_pcd_debug_log_level and get_fsp_mrc_debug_log_level before UPD assignment to get specific control knob assigned by the user.