HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32379
Change subject: src/mb: Use system_reset() ......................................................................
src/mb: Use system_reset()
Use already defined system_reset() function.
Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c 10 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32379/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index c524446..c056ac8f 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -19,6 +19,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/intel/romstage.h> @@ -245,8 +246,7 @@ if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 6727f4a..e9af430 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -19,6 +19,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -214,8 +215,7 @@ if (!s3resume && setup_sio_gpio(c_bsel)) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); }
/* Enable SPD ROMs and DDR-II DRAM */ diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 8ce5979..42336f1 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -16,6 +16,7 @@ */
#include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> @@ -191,8 +192,7 @@ if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); }
sdram_initialize(boot_path, spd_addrmap); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 81669ed..d643b12 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -16,6 +16,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -256,8 +257,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index a356195..7e3b7db 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> @@ -218,8 +219,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 5100735..a7b35a4 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> @@ -52,8 +53,7 @@ RCBA32(BUC) &= ~PCH_DISABLE_GBE; /* Datasheet says clearing the bit requires a reset after */ printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); - outb(0xe, 0xcf9); - halt(); + system_reset(); } #endif
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 05f9d1f..3d01eb1 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <halt.h> #include <arch/io.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> @@ -266,8 +267,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index be71cf4..ea207e8 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -19,6 +19,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -195,8 +196,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 86d94a6..0d68fac 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -19,6 +19,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -196,8 +197,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index efb376c..e85da1f 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -18,6 +18,7 @@
#include <stdint.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -228,8 +229,7 @@
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
/* Perform some early chipset initialization required