[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/espi: Reset eSPI registers to known state

[Furquan Shaikh (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52058 )

Change subject: soc/amd/common/espi: Reset eSPI registers to known state
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Patch Set 4: Code-Review+2

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52058/comment/22de2e8c_8134694a 
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
           : 
           : On Cezanne, the PSP modifies these registers such that the eSPI
> eSPI is interesting because the PSP configures the controller so it can write port80s before jumping […]

Why is the PSP writing to port80?