Boon Tiong Teo (boon.tiong.teo@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976
-gerrit
commit a61b46f185e2b90e3f424dbee5173c5df96cb74c Author: Teo Boon Tiong boon.tiong.teo@intel.com Date: Wed Dec 28 18:56:26 2016 +0800
fsp1_1: Fix boot failure for non-verstage case
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage. So, use the same entry point in either case.
Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong boon.tiong.teo@intel.com --- src/drivers/intel/fsp1_1/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4088293..a3261df 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -28,7 +28,7 @@ romstage-y += fsp_util.c romstage-y += hob.c romstage-y += raminit.c romstage-y += romstage.c -romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S +romstage-y += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c romstage-$(CONFIG_MMA) += mma_core.c