Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49005 )
Change subject: soc/mediatek/mt8192: pmic: update initial setting ......................................................................
soc/mediatek/mt8192: pmic: update initial setting
We found that the switch frequency of vgpu is at 4~5Mhz with high current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A). The switch frequency of vgpu should be kept at 2.5Mhz.
The root cause is that phase config of vcore is not disabled, it will affect the switch frequency of vgpu. Corret the phase setting at initialization.
BUG=b:172636735 BRANCH=none TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49005 Reviewed-by: Yu-Ping Wu yupingso@google.com Reviewed-by: Hung-Te Lin hungte@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index a8e93ca..68af6f2 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -90,6 +90,7 @@ {0x19AE, 0x6E, 0x7E, 0}, {0x19B0, 0x3C00, 0x3C00, 0}, {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x19DE, 0x1, 0x1, 6}, /* RG_VGPUVCORE_PH2_OFF, disable phase 2 */ {0x1A08, 0x4200, 0x4680, 0}, {0x1A0A, 0x6E, 0x7E, 0}, {0x1A0C, 0x3C00, 0x3C00, 0},