[coreboot-gerrit] [XS] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses

[Shuo Liu (Code Review)]

Attention is currently required from: Andrey Petrov, Chen, Gang C, Intel coreboot Reviewers, Julius Werner, Ronak Kanabar, Yu-Ping Wu.

Hello Chen, Gang C,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/86570?usp=email

to review the following change.

Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses
......................................................................

util/cbfstool: Place XIP components and FIT at high flash addresses

By default, CACHE_ROM_SIZE is limited to 16MB, but still covers the
whole CBFS. When CBFS spans larger than 16MB, XIP components and FIT
might be laid outside the cached region.

Place XIP components and FIT as high as possible so that always to
maximize the opportunity for them to being cached.

Change-Id: I8eb469fdcd18d01652979f28049fe1ea3b59311c
Signed-off-by: Shuo Liu 
Signed-off-by: Gang Chen 
---
M Makefile.mk
M src/cpu/intel/fit/Makefile.mk
M src/drivers/intel/fsp2_0/Makefile.mk
M src/security/vboot/Makefile.mk
4 files changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86570/1

diff --git a/Makefile.mk b/Makefile.mk
index bc547de..054ac13 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1371,7 +1371,7 @@
 # If CAR does not support execution of code, romstage on x86 is expected to be
 # xip.
 ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
-$(CONFIG_CBFS_PREFIX)/romstage-options += --xip
+$(CONFIG_CBFS_PREFIX)/romstage-options += --xip -z

# For efficient MTRR utilisation use natural alignment for romstage.
 ifeq ($(CONFIG_SETUP_XIP_CACHE),y)
diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk
index f405c57..7861859 100644
--- a/src/cpu/intel/fit/Makefile.mk
+++ b/src/cpu/intel/fit/Makefile.mk
@@ -12,6 +12,7 @@
 intel_fit-file := fit_table.c:struct
 intel_fit-type := intel_fit
 intel_fit-align := 16
+intel_fit-options := -z

$(call add_intermediate, set_fit_ptr, $(IFITTOOL))
    @printf "    UPDATE-FIT set FIT pointer to table\n"
diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk
index 18a62e3..cce2cba 100644
--- a/src/drivers/intel/fsp2_0/Makefile.mk
+++ b/src/drivers/intel/fsp2_0/Makefile.mk
@@ -72,8 +72,8 @@
 $(FSP_M_CBFS)-type := fsp
 $(FSP_M_CBFS_2)-type := fsp
 ifeq ($(CONFIG_FSP_M_XIP),y)
-$(FSP_M_CBFS)-options := --xip $(TXTIBB)
-$(FSP_M_CBFS_2)-options := --xip $(TXTIBB)
+$(FSP_M_CBFS)-options := --xip $(TXTIBB) -z
+$(FSP_M_CBFS_2)-options := --xip $(TXTIBB) -z
 endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZMA),y)
 $(FSP_M_CBFS)-compression := LZMA
diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk
index e9b3eb6..f1eb54a 100644
--- a/src/security/vboot/Makefile.mk
+++ b/src/security/vboot/Makefile.mk
@@ -166,7 +166,7 @@
 # If CAR does not support execution of code, verstage on x86 is expected to be
 # xip.
 ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
-$(CONFIG_CBFS_PREFIX)/verstage-options += --xip
+$(CONFIG_CBFS_PREFIX)/verstage-options += --xip -z
 endif

endif