Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3823
-gerrit
commit 174f1aee466e4d5903905bb6b6ed98d555b33855 Author: Mike Loptien mike.loptien@se-eng.com Date: Thu Jul 18 10:30:47 2013 -0600
AMD Fam16: Add OSC method to PCI0
This patch is adapted from previously merged changes for Family 14 [1] and Family 15.
The _OSC method is required for PCIe devices and an error is logged to dmesg under Linux if _OSC is not found. _OSC is described in chapter 6.2.9 of the ACPI spec v3.0.
[1] 00a0e76 AMD Fam14 DSDT: Add OSC method
Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a Signed-off-by: Mike Loptien mike.loptien@se-eng.com Reviewed-by: Marc Jones marc.jones@se-eng.com --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 5d3a29c..06b4fe7 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -21,6 +21,25 @@ /* South Bridge */ /* _SB.PCI0 */
+/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + // Create DWord-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + /* Describe the Southbridge devices */
/* 0:11.0 - SATA */