[coreboot-gerrit] [S] Change in coreboot[main]: southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter w...

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85013?usp=email )

Change subject: southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter when writing _PRT table
......................................................................

southbridge/intel/common/acpi_pirq_gen: make PCI scope as parameter when writing _PRT table

Add a scope parameter for `intel_write_pci0_PRT()` so that it could be
reused for multiple domains.

Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/common/block/irq/irq.c
M src/southbridge/intel/common/acpi_pirq_gen.c
M src/southbridge/intel/common/acpi_pirq_gen.h
M src/southbridge/intel/common/rcba_pirq.c
4 files changed, 7 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85013/1

diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c
index 386538e..16d0fa3 100644
--- a/src/soc/intel/common/block/irq/irq.c
+++ b/src/soc/intel/common/block/irq/irq.c
@@ -397,7 +397,7 @@
    	entry = entry->next;
    }

-	intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map);
+	intel_write_pci_PRT("\_SB.PCI0", pin_irq_map, map_count, &pirq_map);
    free(pin_irq_map);

return true;
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c
index 1dadc8e..3b5c3e5 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.c
+++ b/src/southbridge/intel/common/acpi_pirq_gen.c
@@ -43,12 +43,10 @@
    }
 }

-void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map,
-			  unsigned int map_count,
-			  const struct pic_pirq_map *pirq_map)
+void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map,
+			 unsigned int map_count, const struct pic_pirq_map *pirq_map)
 {
-	/* _SB.PCI0._PRT */
-	acpigen_write_scope("\_SB.PCI0");
+	acpigen_write_scope(scope);
    acpigen_write_method("_PRT", 0);
    acpigen_write_if();
    acpigen_emit_namestring("PICM");
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h
index 36e432e..f22e1d4 100644
--- a/src/southbridge/intel/common/acpi_pirq_gen.h
+++ b/src/southbridge/intel/common/acpi_pirq_gen.h
@@ -84,9 +84,8 @@
  * slot/pin combination, and optionally providing paths to LNKx devices that can
  * provide IRQs in PIC mode.
  */
-void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map,
-			  unsigned int map_count,
-			  const struct pic_pirq_map *pirq_map);
+void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map,
+			 unsigned int map_count, const struct pic_pirq_map *pirq_map);

bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
    		  unsigned int map_count, unsigned int slot,
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c
index 956fe63..ae22143 100644
--- a/src/southbridge/intel/common/rcba_pirq.c
+++ b/src/southbridge/intel/common/rcba_pirq.c
@@ -90,7 +90,7 @@
    	map_count++;
    }

-	intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map);
+	intel_write_pci_PRT("\_SB.PCI0", pin_irq_map, map_count, &pirq_map);

free(pin_irq_map);
 }