Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48845 )
Change subject: mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD card ......................................................................
mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD card
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card.
BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 8 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 8d05c32..f612beb 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,8 +5,15 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033"
- # Disable SRCCLKREQ1# and SRCCLKREQ3# + # Disable WLAN PCIE 7 + register "PcieRpEnable[6]" = "0" + register "PcieRpLtrEnable[6]" = "0" register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + + # Disable SD Card PCIE 8 + register "PcieRpEnable[7]" = "0" + register "PcieRpLtrEnable[7]" = "0" + register "PcieRpHotPlug[7]" = "0" register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
device domain 0 on