22 Oct
2020
22 Oct
'20
9:59 p.m.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45713 )
Change subject: sb/intel/lynxpoint/pcie: Fix clock gating routine ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45713/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/45713/2/src/southbridge/intel/lynxp... PS2, Line 286: pci_or_config8(dev, 0x324, 1 << 5);
Yes, it is intentional. The original code was wrong, and the new code matches what the BWG states.
Ack. Maybe add comment what that bit does?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
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