[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Disable S5 wake on LAN by default

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32502

Change subject: mb/google/sarien: Disable S5 wake on LAN by default
......................................................................

mb/google/sarien: Disable S5 wake on LAN by default

Chromebook doesn't require support wake on LAN in S5.
Disable it by default for power saving.

BUG=b:131571666
TEST= check LAN indicator is off under S5

Signed-off-by: Eric Lai 
Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03
---
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
3 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/32502/1

diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 96146ba..0cdd9d0 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -52,6 +52,9 @@
    # Enable DDC for DDI port B
    register "DdiPortBDdc" = "1"

+	register "LanWakeFromDeepSx" = "0"
+	register "WolEnableOverride" = "0"
+
    # VR Settings Configuration for 4 Domains
    #+----------------+-------+-------+-------+-------+
    #| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9bba226..ca44085 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -400,6 +400,8 @@

/* Unlock all GPIO Pads */
    uint8_t PchUnlockGpioPads;
+	uint8_t LanWakeFromDeepSx;
+	uint8_t WolEnableOverride;
 };

typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 61d2520..cc01d10 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -212,6 +212,10 @@
    params->DdiPortDDdc = config->DdiPortDDdc;
    params->DdiPortFDdc = config->DdiPortFDdc;

+	/* WOL */
+	params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
+	params->PchPmWolEnableOverride = config->WolEnableOverride;
+
    /* S0ix */
    params->PchPmSlpS0Enable = config->s0ix_enable;