Attention is currently required from: Damien Zammit, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51874 )
Change subject: nb/intel/x4x: Reflow long lines ......................................................................
nb/intel/x4x: Reflow long lines
Try to unbreak long lines and user-visible strings.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c 6 files changed, 133 insertions(+), 254 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51874/1
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index eab5365..afb7742 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -8,8 +8,7 @@ #include "raminit.h" #include "x4x.h"
-static void print_dll_setting(const struct dll_setting *dll_setting, - u8 default_verbose) +static void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose) { u8 debug_level = default_verbose ? BIOS_DEBUG : RAM_DEBUG;
@@ -75,11 +74,9 @@
static const u8 max_tap[3] = {12, 10, 13};
-static int increment_dq_dqs(const struct sysinfo *s, - struct dll_setting *dq_dqs_setting) +static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) { - u8 max_tap_val = max_tap[s->selected_timings.mem_clk - - MEM_CLOCK_800MHz]; + u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi < 6) { dq_dqs_setting->pi += 1; @@ -102,11 +99,9 @@ return CB_SUCCESS; }
-static int decrement_dq_dqs(const struct sysinfo *s, - struct dll_setting *dq_dqs_setting) +static int decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) { - u8 max_tap_val = max_tap[s->selected_timings.mem_clk - - MEM_CLOCK_800MHz]; + u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi > 0) { dq_dqs_setting->pi -= 1; @@ -159,8 +154,7 @@ FAILING = 1 };
-static u8 test_dq_aligned(const struct sysinfo *s, - const u8 channel) +static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel) { u32 address; int rank, lane; @@ -174,17 +168,14 @@ for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) { if ((count1 % 16) == 0) MCHBAR32(0xf90) = 1; - const u32 pattern = - write_training_schedule[count1]; + const u32 pattern = write_training_schedule[count1]; write32((u32 *)address + 8 * count1, pattern); - write32((u32 *)address + 8 * count1 + 4, - pattern); + write32((u32 *)address + 8 * count1 + 4, pattern); }
const u32 good = write_training_schedule[count]; write32(&data[0], read32((u32 *)address + 8 * count)); - write32(&data[4], - read32((u32 *)address + 8 * count + 4)); + write32(&data[4], read32((u32 *)address + 8 * count + 4)); FOR_EACH_BYTELANE(lane) { u8 expected = (good >> ((lane % 4) * 8)) & 0xff; if (data[lane] != expected) @@ -235,8 +226,8 @@ success_mask &= ~(1 << lane); } if (status == CB_ERR) { - printk(BIOS_CRIT, "Could not find a case of %s " - "writes on CH%d, lane %d\n", + printk(BIOS_CRIT, + "Could not find a case of %s writes on CH%d, lane %d\n", expected_result == FAILING ? "failing" : "succeeding", channel, lane); return CB_ERR; @@ -281,19 +272,15 @@ /* Start from DQS settings */ memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting));
- if (find_dq_limit(s, channel, dq_setting, dq_lower, - SUCCEEDING)) { - printk(BIOS_CRIT, - "Could not find working lower limit DQ setting\n"); + if (find_dq_limit(s, channel, dq_setting, dq_lower, SUCCEEDING)) { + printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n"); return CB_ERR; }
memcpy(dq_upper, dq_lower, sizeof(dq_lower));
- if (find_dq_limit(s, channel, dq_setting, dq_upper, - FAILING)) { - printk(BIOS_WARNING, - "Could not find failing upper limit DQ setting\n"); + if (find_dq_limit(s, channel, dq_setting, dq_upper, FAILING)) { + printk(BIOS_WARNING, "Could not find failing upper limit DQ setting\n"); return CB_ERR; }
@@ -302,8 +289,8 @@ dq_upper[lane] -= CONSISTENCY - 1; u8 dq_center = (dq_upper[lane] + dq_lower[lane]) / 2;
- printk(RAM_DEBUG, "Centered value for DQ DLL:" - " ch%d, lane %d, #steps = %d\n", + printk(RAM_DEBUG, + "Centered value for DQ DLL: ch%d, lane %d, #steps = %d\n", channel, lane, dq_center); for (i = 0; i < dq_center; i++) { /* Should never happen */ @@ -403,13 +390,10 @@ }
if (expected_result == SUCCEEDING) { - printk(BIOS_CRIT, - "Could not find RT DQS setting\n"); + printk(BIOS_CRIT, "Could not find RT DQS setting\n"); return CB_ERR; } else { - printk(RAM_DEBUG, - "Read succeeded over all DQS" - " settings, continuing\n"); + printk(RAM_DEBUG, "Read succeeded over all DQS settings, continuing\n"); return CB_SUCCESS; } } @@ -664,8 +648,7 @@ if (bytelane_ok & (1 << lane)) continue;
- printk(RAM_SPEW, "%d, %d, %02d, %d," - " lane%d sample: %d\n", + printk(RAM_SPEW, "%d, %d, %02d, %d, lane%d sample: %d\n", dqs_setting[lane].coarse, dqs_setting[lane].clk_delay, dqs_setting[lane].tap, @@ -785,8 +768,7 @@ printk(BIOS_DEBUG, "\tCH%d\n", ch); config = chanconfig_lut[s->dimm_config[ch]];
- MCHBAR8(0x5d8 + 0x400 * ch) = - MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e; + MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e; MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & ~0x3fff) | 0x3fff; MCHBAR8(0x265 + 0x400 * ch) = @@ -803,12 +785,9 @@ MCHBAR8(0x298 + 2 + 0x400 * ch) = (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f) | odt_force[config][rank0]; - MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) - & ~0x7e) | 0x4e; - MCHBAR8(0x5d9 + 0x400 * ch) = - (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04; - MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) - | 0x00014000; + MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e; + MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04; + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
if (increment_to_dqs_edge(s, ch, rank0)) die("Write Leveling failed!"); @@ -827,8 +806,7 @@ set_rank_write_level(s, ch, config, rank0, rank0, 0); send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
- MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) - & ~0x0e) | 0x0e; + MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e; MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & ~0x3fff) | 0x1807; MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 6170e41..dced902 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -18,8 +18,7 @@ /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) { - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, - 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + static const u16 ggc2uma[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352};
if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); @@ -30,7 +29,7 @@ /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ u32 decode_igd_gtt_size(const u32 gsm) { - static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + static const u8 ggc2gtt[] = {0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
if (gsm >= ARRAY_SIZE(ggc2gtt)) die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index de60338..2245f96 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -41,8 +41,7 @@ tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; tom <<= 26;
- printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom);
tomk = tolud >> 10;
@@ -77,8 +76,7 @@ tomk -= delta_cbmem; uma_sizek += delta_cbmem;
- printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", - delta_cbmem); + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem);
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
@@ -101,8 +99,8 @@ (touud - top32memk) >> 10); }
- printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", tomk << 10, uma_sizek << 10); + printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n", + tomk << 10, uma_sizek << 10); uma_resource(dev, index++, tomk, uma_sizek);
/* Reserve high memory where the NB BARs are up to 4GiB */ diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8ff0ffc..58c34ad 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -34,8 +34,7 @@ return spd_ddr3_calc_unique_crc(raw_spd, len); }
-static enum cb_err verify_spds(const u8 *spd_map, - const struct sysinfo *ctrl_cached) +static enum cb_err verify_spds(const u8 *spd_map, const struct sysinfo *ctrl_cached) { int i; u16 crc; @@ -44,11 +43,9 @@ if (!(spd_map[i])) continue; int len = smbus_read_byte(spd_map[i], 0); - if (len < 0 && ctrl_cached->dimms[i].card_type - == RAW_CARD_UNPOPULATED) + if (len < 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED) continue; - if (len > 0 && ctrl_cached->dimms[i].card_type - == RAW_CARD_UNPOPULATED) + if (len > 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED) return CB_ERR;
if (ctrl_cached->spd_type == DDR2) @@ -79,8 +76,7 @@
#define CTRL_MIN_TCLK_DDR2 TCK_400MHZ
-static void select_cas_dramfreq_ddr2(struct sysinfo *s, - const struct abs_timings *saved_timings) +static void select_cas_dramfreq_ddr2(struct sysinfo *s, const struct abs_timings *saved_timings) { u8 try_cas; /* Currently only these CAS are supported */ @@ -152,8 +148,7 @@
if (!(decoded_dimm.width & (0x08 | 0x10))) {
- printk(BIOS_ERR, - "DIMM%d Unsupported width: x%d. Disabling dimm\n", + printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n", dimm_idx, s->dimms[dimm_idx].width); return CB_ERR; } @@ -166,8 +161,7 @@ * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' * The formula is pagesize in KiB = width * 2^col_bits / 8. */ - s->dimms[dimm_idx].page_size = decoded_dimm.width * - (1 << decoded_dimm.col_bits) / 8; + s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8;
switch (decoded_dimm.banks) { case 4: @@ -177,8 +171,7 @@ s->dimms[dimm_idx].n_banks = N_BANKS_8; break; default: - printk(BIOS_ERR, - "DIMM%d Unsupported #banks: x%d. Disabling dimm\n", + printk(BIOS_ERR, "DIMM%d Unsupported #banks: x%d. Disabling dimm\n", dimm_idx, decoded_dimm.banks); return CB_ERR; } @@ -189,22 +182,14 @@
saved_timings->cas_supported &= decoded_dimm.cas_supported;
- saved_timings->min_tRAS = - MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); - saved_timings->min_tRP = - MAX(saved_timings->min_tRP, decoded_dimm.tRP); - saved_timings->min_tRCD = - MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); - saved_timings->min_tWR = - MAX(saved_timings->min_tWR, decoded_dimm.tWR); - saved_timings->min_tRFC = - MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); - saved_timings->min_tWTR = - MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); - saved_timings->min_tRRD = - MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); - saved_timings->min_tRTP = - MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); + saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); + saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP); + saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); + saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR); + saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); + saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); + saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); + saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); for (i = 0; i < 8; i++) { if (!(saved_timings->cas_supported & (1 << i))) saved_timings->min_tCLK_cas[i] = 0; @@ -231,8 +216,7 @@ *tCLK = 0; }
-static void select_cas_dramfreq_ddr3(struct sysinfo *s, - struct abs_timings *saved_timings) +static void select_cas_dramfreq_ddr3(struct sysinfo *s, struct abs_timings *saved_timings) { /* * various constraints must be fulfilled: @@ -278,9 +262,9 @@
min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); if (min_tCLK == 0) { - printk(BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz " - "as last resort"); + printk(BIOS_ERR, + "DRAM frequency is under lowest supported frequency (400 MHz). " + "Increasing to 400 MHz as last resort"); min_tCLK = TCK_400MHZ; }
@@ -337,8 +321,7 @@ if (s->spd_type == DDR2) return; /* Does not matter if only one channel is populated */ - if (!CHANNEL_IS_POPULATED(s->dimms, 0) - || !CHANNEL_IS_POPULATED(s->dimms, 1)) + if (!CHANNEL_IS_POPULATED(s->dimms, 0) || !CHANNEL_IS_POPULATED(s->dimms, 1)) return; if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) return; @@ -373,8 +356,7 @@ * for all densities except the 256Mb device, which has a 1KB page size." * Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' */ - s->dimms[dimm_idx].page_size = decoded_dimm.width * - (1 << decoded_dimm.col_bits) / 8; + s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8;
s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */
@@ -382,61 +364,40 @@ s->dimms[dimm_idx].rows = decoded_dimm.row_bits; s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
- saved_timings->min_tRAS = - MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); - saved_timings->min_tRP = - MAX(saved_timings->min_tRP, decoded_dimm.tRP); - saved_timings->min_tRCD = - MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); - saved_timings->min_tWR = - MAX(saved_timings->min_tWR, decoded_dimm.tWR); - saved_timings->min_tRFC = - MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); - saved_timings->min_tWTR = - MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); - saved_timings->min_tRRD = - MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); - saved_timings->min_tRTP = - MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); - saved_timings->min_tAA = - MAX(saved_timings->min_tAA, decoded_dimm.tAA); + saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); + saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP); + saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); + saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR); + saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); + saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); + saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); + saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); + saved_timings->min_tAA = MAX(saved_timings->min_tAA, decoded_dimm.tAA); saved_timings->cas_supported &= decoded_dimm.cas_supported;
- s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, - raw_spd[0]); + s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, raw_spd[0]);
s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored;
return CB_SUCCESS; }
-static void select_discrete_timings(struct sysinfo *s, - const struct abs_timings *timings) +static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings) { - s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, - s->selected_timings.tclk); - s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, - s->selected_timings.tclk); - s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, - s->selected_timings.tclk); - s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, - s->selected_timings.tclk); - s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC, - s->selected_timings.tclk); - s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR, - s->selected_timings.tclk); - s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD, - s->selected_timings.tclk); - s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP, - s->selected_timings.tclk); + s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, s->selected_timings.tclk); + s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, s->selected_timings.tclk); + s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, s->selected_timings.tclk); + s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, s->selected_timings.tclk); + s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC, s->selected_timings.tclk); + s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR, s->selected_timings.tclk); + s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD, s->selected_timings.tclk); + s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP, s->selected_timings.tclk); } static void print_selected_timings(struct sysinfo *s) { printk(BIOS_DEBUG, "Selected timings:\n"); - printk(BIOS_DEBUG, "\tFSB: %dMHz\n", - fsb_to_mhz(s->selected_timings.fsb_clk)); - printk(BIOS_DEBUG, "\tDDR: %dMHz\n", - ddr_to_mhz(s->selected_timings.mem_clk)); + printk(BIOS_DEBUG, "\tFSB: %dMHz\n", fsb_to_mhz(s->selected_timings.fsb_clk)); + printk(BIOS_DEBUG, "\tDDR: %dMHz\n", ddr_to_mhz(s->selected_timings.mem_clk));
printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); @@ -505,8 +466,8 @@
printk(BIOS_DEBUG, "Decoding dimm %d\n", i); if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) { - printk(BIOS_DEBUG, "i2c block operation failed," - " trying smbus byte operation.\n"); + printk(BIOS_DEBUG, + "i2c block operation failed, trying smbus byte operation.\n"); for (j = 0; j < 128; j++) raw_spd[j] = smbus_read_byte(device, j); } @@ -514,16 +475,14 @@ if (s->spd_type == DDR2){ if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) { printk(BIOS_WARNING, - "Encountered problems with SPD, " - "skipping this DIMM.\n"); + "Encountered problems with SPD, skipping this DIMM.\n"); s->dimms[i].card_type = RAW_CARD_UNPOPULATED; continue; } } else { /* DDR3 */ if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) { printk(BIOS_WARNING, - "Encountered problems with SPD, " - "skipping this DIMM.\n"); + "Encountered problems with SPD, skipping this DIMM.\n"); /* something in decoded SPD was unsupported */ s->dimms[i].card_type = RAW_CARD_UNPOPULATED; continue; @@ -560,11 +519,9 @@ else die("Dual-rank x16 not supported\n"); } - s->dimm_config[chan] |= - dimm_config << (i % DIMMS_PER_CHANNEL) * 2; + s->dimm_config[chan] |= dimm_config << (i % DIMMS_PER_CHANNEL) * 2; } - printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, - s->dimm_config[chan]); + printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]); }
} @@ -577,11 +534,9 @@ if (boot_path >= 1) { pmsts = MCHBAR32(PMSTS_MCHBAR); if (!(pmsts & 1)) - printk(BIOS_DEBUG, - "Channel 0 possibly not in self refresh\n"); + printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n"); if (!(pmsts & 2)) - printk(BIOS_DEBUG, - "Channel 1 possibly not in self refresh\n"); + printk(BIOS_DEBUG, "Channel 1 possibly not in self refresh\n"); }
pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); @@ -638,8 +593,8 @@ /* check SPD checksum to make sure the DIMMs haven't been replaced */ fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS; if (!fast_boot) { - printk(BIOS_DEBUG, "SPD checksums don't match," - " dimm's have been replaced\n"); + printk(BIOS_DEBUG, + "SPD checksums don't match, dimm's have been replaced\n"); } else { find_fsb_speed(&s); fast_boot = s.max_fsb == ctrl_cached->max_fsb; @@ -667,8 +622,7 @@
/* Detect dimms per channel */ reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); - printk(BIOS_DEBUG, "Dimms per channel: %d\n", - (reg8 & 0x10) ? 1 : 2); + printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2);
mchinfo_ddr2(&s);
@@ -692,8 +646,7 @@
cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - &s, sizeof(s)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &s, sizeof(s));
if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 1bfeaad..84dbff5 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -367,8 +367,7 @@ } }
-void rt_set_dqs(u8 channel, u8 lane, u8 rank, - struct rt_dqs_setting *dqs_setting) +void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting) { u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); @@ -525,12 +524,10 @@ reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; if (s->spd_type == DDR2) reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk - - MEM_CLOCK_667MHz][reg8][pagemod] - << 22; + - MEM_CLOCK_667MHz][reg8][pagemod] << 22; else reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk - - MEM_CLOCK_800MHz][reg8][pagemod] - << 22; + - MEM_CLOCK_800MHz][reg8][pagemod] << 22; } MCHBAR32(0x400*i + 0x252) = reg32;
@@ -675,8 +672,7 @@ u16 reg16 = 0; u32 reg32 = 0;
- const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, - 0x08, 0x10 }; + const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 };
MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); @@ -718,8 +714,7 @@ udelay(1); /* 533ns */
/* ME related */ - MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, - s->spd_type == DDR2 ? 0x551803 : 0x555801); + MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801);
MCHBAR16_AND(0x1b4, ~0x800); if (s->spd_type == DDR2) { @@ -750,34 +745,25 @@
if (s->spd_type == DDR2) { if (!CHANNEL_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, - "No dimms in channel %d\n", i); + printk(BIOS_DEBUG, "No dimms in channel %d\n", i); reg8 = 0x3f; } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, - "DimmA populated only in channel %d\n", - i); + printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); reg8 = 0x38; } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, - "DimmB populated only in channel %d\n", - i); + printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); reg8 = 0x7; } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, - "Both dimms populated in channel %d\n", - i); + printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); reg8 = 0; } else { die("Unhandled case\n"); } - MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, - (u32)(reg8 << 24)); + MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, (u32)(reg8 << 24));
} else { /* DDR3 */ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { - MCHBAR8_AND(0x400 * i + 0x5a0 + 3, - ~rank2clken[r + i * 4]); + MCHBAR8_AND(0x400 * i + 0x5a0 + 3, ~rank2clken[r + i * 4]); } } } /* END EACH CHANNEL */ @@ -798,10 +784,8 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); - MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, - s->spd_type == DDR2 ? 0x70 : 0x60); - MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff, - s->spd_type == DDR2 ? 0x5555 : 0xa955); + MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, s->spd_type == DDR2 ? 0x70 : 0x60); + MCHBAR16_AND_OR(0x400*i + 0x590, 0, s->spd_type == DDR2 ? 0x5555 : 0xa955); }
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { @@ -1025,8 +1009,7 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { FOR_EACH_BYTELANE(lane) { FOR_EACH_RANK_IN_CHANNEL(rank) { - rt_set_dqs(ch, lane, rank, - &s->rt_dqs[ch][lane]); + rt_set_dqs(ch, lane, rank, &s->rt_dqs[ch][lane]); } dqsset(ch, lane, &s->dqs_settings[ch][lane]); dqset(ch, lane, &s->dq_settings[ch][lane]); @@ -1117,8 +1100,7 @@ MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]);
/* Override command group strength multiplier */ - if (s->spd_type == DDR3 && - BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { + if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc); } MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); @@ -1186,15 +1168,11 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { if (s->spd_type == DDR2) { - MCHBAR16(0x400 * i + 0x298) = - ddr2_odt[s->dimm_config[i]][1]; - MCHBAR16(0x400 * i + 0x294) = - ddr2_odt[s->dimm_config[i]][0]; + MCHBAR16(0x400 * i + 0x298) = ddr2_odt[s->dimm_config[i]][1]; + MCHBAR16(0x400 * i + 0x294) = ddr2_odt[s->dimm_config[i]][0]; } else { - MCHBAR16(0x400 * i + 0x298) = - ddr3_odt[s->dimm_config[i]][1]; - MCHBAR16(0x400 * i + 0x294) = - ddr3_odt[s->dimm_config[i]][0]; + MCHBAR16(0x400 * i + 0x298) = ddr3_odt[s->dimm_config[i]][1]; + MCHBAR16(0x400 * i + 0x294) = ddr3_odt[s->dimm_config[i]][0]; } u16 reg16 = MCHBAR16(0x400*i + 0x29c); reg16 &= ~0xfff; @@ -1445,11 +1423,9 @@ MCHBAR32(0x400 * channel + 0x248) = reg32;
FOR_EACH_BYTELANE(lane) { - medium |= s->rcven_t[channel].medium[lane] - << (lane * 2); + medium |= s->rcven_t[channel].medium[lane] << (lane * 2); coarse_offset |= - (s->rcven_t[channel].coarse_offset[lane] & 0x3) - << (lane * 2); + (s->rcven_t[channel].coarse_offset[lane] & 0x3) << (lane * 2);
pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4); pi_tap &= ~0x7f; @@ -1546,11 +1522,9 @@ } }
- if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || - ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) MCHBAR8_OR(0x260, 1); - if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || - ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) MCHBAR8_OR(0x660, 1);
/* DRB */ @@ -1659,17 +1633,14 @@ single_channel_offset = 0; } else if (size_me == 0) { if (size_ch0 > size_ch1) - single_channel_offset = dual_channel_size / 2 - + single_channel_size; + single_channel_offset = dual_channel_size / 2 + single_channel_size; else single_channel_offset = dual_channel_size / 2; } else { if ((size_ch0 > size_ch1) && ((map & 0x7) == 4)) - single_channel_offset = dual_channel_size / 2 - + single_channel_size; + single_channel_offset = dual_channel_size / 2 + single_channel_size; else - single_channel_offset = dual_channel_size / 2 - + size_me; + single_channel_offset = dual_channel_size / 2 + size_me; }
MCHBAR16(0x108) = single_channel_offset; @@ -1683,8 +1654,7 @@ u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u32 mmiostart, umasizem; u16 ggc; - u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, - 160, 224, 352 }; + u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
ggc = pci_read_config16(HOST_BRIDGE, 0x52); @@ -1721,10 +1691,8 @@ pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); if (reclaim) { - pci_write_config16(HOST_BRIDGE, 0x98, - (u16)(reclaimbase >> 6)); - pci_write_config16(HOST_BRIDGE, 0x9a, - (u16)(reclaimlimit >> 6)); + pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6)); + pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6)); } pci_write_config16(HOST_BRIDGE, 0xa2, touud); pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); @@ -2091,18 +2059,15 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { reg32 = (2 << 18); reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] - [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] - << 13; + [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] << 13; if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && ch == 1) { reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] - [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - - 1) << 8; + [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - 1) << 8; } else { reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] - [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - << 8; + [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8; } MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); MCHBAR8_AND(0x400*ch + 0x274, ~0x80); @@ -2186,11 +2151,9 @@ * and is only needed in case of ME being used. */ if (ME_UMA_SIZEMB != 0) { - if (RANK_IS_POPULATED(s->dimms, 0, 0) - || RANK_IS_POPULATED(s->dimms, 1, 0)) + if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0)) MCHBAR8_OR(0xa2f, 1 << 0); - if (RANK_IS_POPULATED(s->dimms, 0, 1) - || RANK_IS_POPULATED(s->dimms, 1, 1)) + if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1)) MCHBAR8_OR(0xa2f, 1 << 1); MCHBAR32_OR(0xa30, 1 << 26); } diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 1f49beb..c79fdc3 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -42,15 +42,13 @@ return (MCHBAR8(sample_offset) >> 6) & 1; }
-static void program_timing(const struct rec_timing *timing, u8 channel, - u8 lane) +static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane) { u32 reg32; u16 reg16; u8 reg8;
- printk(RAM_SPEW, " Programming timings:" - "Coarse: %d, Medium: %d, TAP: %d, PI: %d\n", + printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n", timing->coarse, timing->medium, timing->tap, timing->pi);
reg32 = MCHBAR32(0x400 * channel + 0x248); @@ -122,15 +120,12 @@ return 0; }
-static int decr_coarse_low(u8 channel, u8 lane, u32 addr, - struct rec_timing *timing) +static int decr_coarse_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) { - printk(RAM_DEBUG, - " Decreasing coarse until high to low transition is found\n"); + printk(RAM_DEBUG, " Decreasing coarse until high to low transition is found\n"); while (sampledqs(addr, lane, channel) != DQS_LOW) { if (timing->coarse == 0) { - printk(BIOS_CRIT, - "Couldn't find DQS-high 0 indicator, halt\n"); + printk(BIOS_CRIT, "Couldn't find DQS-high 0 indicator, halt\n"); return -1; } timing->coarse--; @@ -141,11 +136,9 @@ return 0; }
-static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, - struct rec_timing *timing) +static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) { - printk(RAM_DEBUG, - " Increasing TAP until low to high transition is found\n"); + printk(RAM_DEBUG, " Increasing TAP until low to high transition is found\n"); /* * We use a do while loop since it happens that the strobe read * is inconsistent, with the strobe already high. The current @@ -164,8 +157,7 @@ } do { if (increase_tap(timing)) { - printk(BIOS_CRIT, - "Could not find DQS-high on fine search.\n"); + printk(BIOS_CRIT, "Could not find DQS-high on fine search.\n"); return -1; } program_timing(timing, channel, lane); @@ -176,15 +168,13 @@ return 0; }
-static int find_dqs_low(u8 channel, u8 lane, u32 addr, - struct rec_timing *timing) +static int find_dqs_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) { /* Look for DQS low, using quarter steps. */ printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n"); while (sampledqs(addr, lane, channel) != DQS_LOW) { if (increase_medium(timing)) { - printk(BIOS_CRIT, - "Coarse > 15: DQS tuning failed, halt\n"); + printk(BIOS_CRIT, "Coarse > 15: DQS tuning failed, halt\n"); return -1; } program_timing(timing, channel, lane); @@ -200,8 +190,7 @@ printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n"); while (sampledqs(addr, lane, channel) != DQS_HIGH) { if (increase_medium(timing)) { - printk(BIOS_CRIT, - "Coarse > 16: DQS tuning failed, halt\n"); + printk(BIOS_CRIT, "Coarse > 16: DQS tuning failed, halt\n"); return -1; } program_timing(timing, channel, lane); @@ -344,8 +333,7 @@ timing[lane].tap = 0; timing[lane].pi = 0;
- if (calibrate_receive_enable(channel, lane, addr, - &timing[lane])) + if (calibrate_receive_enable(channel, lane, addr, &timing[lane])) die("Receive enable calibration failed\n"); if (mincoarse > timing[lane].coarse) mincoarse = timing[lane].coarse; @@ -359,8 +347,8 @@ reg8 = 0; else reg8 = timing[lane].coarse - mincoarse; - printk(BIOS_DEBUG, "ch %d lane %d: coarse offset: %d;" - "medium: %d; tap: %d\n", + printk(BIOS_DEBUG, + "ch %d lane %d: coarse offset: %d;medium: %d; tap: %d\n", channel, lane, reg8, timing[lane].medium, timing[lane].tap); s->rcven_t[channel].coarse_offset[lane] = reg8;