[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )

Change subject: arch/x86: Cache the TSEG region at the top of ram
......................................................................

Patch Set 4:
> Patch Set 4:
>
> I don't think we should do this unconditionally. I think it's going to depend on CAR implementation and uarch -- it's platform dependent, and we know that the current code doesn't explicitly flush all DRAM it's touching during loading.

Do you mean, we should check if TSEG_STAGE_CACHE Kconfig is enable by platform, if yes then only cache tseg region else not ? thus might be good feedback.

I thought keeping inside common x86 code might help platform to call the required function ?