Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57610 )
Change subject: soc/intel/alderlake: Add CPU ID 0x906a4 ......................................................................
soc/intel/alderlake: Add CPU ID 0x906a4
TEST=Build and boot brya
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Varshit B Pandya varshit.b.pandya@intel.com --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c 3 files changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Varshit B Pandya: Looks good to me, but someone else must approve
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 8d03d75..5314076 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -54,5 +54,6 @@ #define CPUID_ALDERLAKE_A0 0x906a0 #define CPUID_ALDERLAKE_A1 0x906a1 #define CPUID_ALDERLAKE_A2 0x906a2 +#define CPUID_ALDERLAKE_A3 0x906a4
#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index a053c70..2fc8eab 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -26,6 +26,7 @@ { CPUID_ALDERLAKE_A0, "Alderlake Platform" }, { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, + { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, };
static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 54eeb3c..4a429ab 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -71,6 +71,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A1 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A2 }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A3 }, { 0, 0 }, };