Hello Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian, Justin TerAvest, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31172
to look at the new patch set (#2).
Change subject: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables ......................................................................
soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL.
This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port.
BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/apollolake/acpi/xhci.asl A src/soc/intel/apollolake/acpi/xhci_apl_ports.asl A src/soc/intel/apollolake/acpi/xhci_glk_ports.asl M src/soc/intel/apollolake/chip.c 4 files changed, 77 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31172/2