Peichao Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33824 )
Change subject: mainboard/google/hatch: create akemi variant. ......................................................................
Patch Set 20:
Patch Set 19:
Patch Set 19:
Patch Set 19:
Sorry Peichao, because of the rebase, there are a few changes that need to be made:
override_early_gpio_table() is now variant_early_gpio_table() AND
it needs to contain ALL of the early GPIOs needed by the board, because of a quirk in the way the override- code works. I haven't taken a look at the Akemi schematic yet, but depending on how closely you followed the reference schematic, these are probably the items you need to add to the early_gpio_table:
/* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* B17 : H1_SLAVE_SPI_MISO_R */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), /* F11 : PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* F20 : PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F20, NONE, PLTRST), /* F21 : PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_F21, NONE, PLTRST), /* F22 : PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
Copy that, let me do it
Oops, I mean minus the PCH_MEM_STRAP pins; they don't need to be included in the early_gpio_table.
We will use below GPIOs for memory strap. your mean don't include them in the early_gpio_table? right? Thanks. /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ PAD_CFG_GPI(GPP_F10, NONE, PLTRST), /* H19 : MEM_STRAP_0 */ PAD_CFG_GPI(GPP_H19, NONE, PLTRST), /* H22 : MEM_STRAP_1 */ PAD_CFG_GPI(GPP_H22, NONE, PLTRST),