[coreboot-gerrit] Change in coreboot[master]: nb/intel/i440bx: Add PMCR register to ACPI code

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41092 )

Change subject: nb/intel/i440bx: Add PMCR register to ACPI code
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nb/intel/i440bx: Add PMCR register to ACPI code

p3b-f suspend code is going to use it.

Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui 
---
M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41092/1

diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index fa5948f..476be30 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -10,6 +10,8 @@
    {
    	Offset (0x67),	// DRB7
    	DRB7,	8,
+		Offset (0x7A),	// PMCR
+		PMCR,	8
    }
    Method(TOM1, 0) {
    	/* Multiply by 8MB to get TOM */