[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7

[Michael Niewöhner (Code Review)]

Hello Patrick Rudolph, Subrata Banik, build bot (Jenkins), Nico Huber, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36339

to look at the new patch set (#4).

Change subject: soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7
......................................................................

soc/intel/skylake: lock chipset BAR registers via MSR 0x2E7

Set MSR 0x2e7 in any case at the end of POST to lock most of the chipset
BAR registers in accordance to Intel BWG.

Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/icelake/finalize.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/skylake/finalize.c
7 files changed, 26 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36339/4