[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/13/src/soc/intel/cannonlake/r... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/13/src/soc/intel/cannonlake/r... 
PS13, Line 159: 	top_of_ram -= top_of_ram_size;
> didn't get this part. […]

CB:35029 will hopefully address this concern