[coreboot-gerrit] Change in coreboot[master]: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table

[Hsuan-ting Chen (Code Review)]

Attention is currently required from: Hsuan Ting Chen.
Hello Hsuan Ting Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/58156

to review the following change.

Change subject: [WIP] mainboard/google: Add EC_IN_RW to the early gpio table
......................................................................

[WIP] mainboard/google: Add EC_IN_RW to the early gpio table

vboot_reference is introducing a new field (ctx) to store the current
boot mode. This boot mode needs to be decided at verstage in coreboot.

We need the pin EC_IN_RW in deciding the bootmode, so we moved this pin
to early gpios, which will be configured at bootblock.

This change applies on the following platforms:
- brya
- [TBA]

This CL will be squashed into the main boot mode change after finishing.

Signed-off-by: Hsuan Ting Chen 
Change-Id: Ib1bd26b0ed7c0ff23b5fbfa1b641c092c25f921c
---
M 3rdparty/chromeec
M 3rdparty/vboot
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
4 files changed, 6 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58156/1

diff --git a/3rdparty/chromeec b/3rdparty/chromeec
index 4c21b57..f48b299 160000
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
@@ -1 +1 @@
-Subproject commit 4c21b57eb9619cc3dc86d11226917d25f62f1bc8
+Subproject commit f48b29920036c69793eb1fdca0af7f8d945a20ab
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 13f601f..2cf7657 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 13f601fbd4c1b128f333391e4552082594f0ff25
+Subproject commit 2cf76574dbf57c70da3a835f2a45d5619dc058f5
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index 777b816..8e51126 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -390,6 +390,8 @@
    PAD_CFG_GPO(GPP_D11, 1, DEEP),
    /* E15 : RSVD_TP ==> PCH_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
    /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index 73fad72..7eff064 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -414,6 +414,8 @@
    PAD_CFG_GPO(GPP_E16, 0, DEEP),
    /* E15 : RSVD_TP ==> PCH_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
    /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
    PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
    /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */