Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59585 )
Change subject: soc/amd/*: PSP verstage minbuild ......................................................................
soc/amd/*: PSP verstage minbuild
The PSP that is supplied for Picasso AMD-based chromebooks currently requires a psp_verstage to boot. This supplies a minimal psp verstage that does the initialization that's normally done there, then exits without doing any verification.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: Ie506193d21207ecabe65158e84dc02eec1cf5b26 --- M src/arch/x86/car.ld M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/Kconfig M src/soc/amd/common/psp_verstage/psp_verstage.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 6 files changed, 73 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/59585/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 5a46b8b..878a7da 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -13,7 +13,7 @@ * aligned when using this option. */ REGION(pagetables, ., 4K * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4K) #endif -#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) +#if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) || CONFIG(MIN_PSP_VSTAGE)) /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ VBOOT2_WORK(., 12K) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 6c8c3e5..f3e4017 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -388,7 +388,7 @@
config PSP_VERSTAGE_FILE string "Specify the PSP_verstage file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK || MIN_PSP_VSTAGE default "$(obj)/psp_verstage.bin" help Add psp_verstage file to the build & PSP Directory Table diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 834abaa..38ee92c 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -5,3 +5,13 @@ Configure PSP Verstage to use Crypto Co-processor (CCP) DMA while accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. + +config MIN_PSP_VSTAGE + bool "Use minimal psp 'verstage' that doesn't do verification" + depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2 + default y if !VBOOT && MAINBOARD_HAS_CHROMEOS + help + Build and load a minimal "verstage" that does the initialization + as normal, but skips the verification portion of verstage. This + is needed for booting Picasso/Dali based chromebooks when not using + verstage. diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 71f07c0..5a55ac1 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -206,6 +206,35 @@ return 0; }
+/* + * Save workbuf (and soon memory console and timestamps) to the bootloader to pass + * back to coreboot. + */ +static uint32_t save_min_buffers(void) +{ + uint32_t retval; + uint32_t buffer_size = MIN_TRANSFER_BUFFER_SIZE; + struct transfer_info_struct buffer_info = {0}; + + + buffer_info.magic_val = TRANSFER_MAGIC_VAL; + buffer_info.struct_bytes = sizeof(buffer_info); + buffer_info.buffer_size = buffer_size; + buffer_info.workbuf_offset = (uint32_t)((uintptr_t)_fmap_cache - + (uintptr_t)_vboot2_work); + + memset(_transfer_buffer,0,buffer_size); + memcpy(_transfer_buffer, &buffer_info, sizeof(buffer_info)); + + retval = save_uapp_data((void *)_transfer_buffer, buffer_size); + if (retval) { + printk(BIOS_ERR, "Error: Could not save workbuf. Error code 0x%08x\n", retval); + return POSTCODE_WORKBUF_SAVE_ERROR; + } + + return 0; +} + void Main(void) { uint32_t retval; @@ -226,7 +255,8 @@
svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); - if (retval) { + + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && retval) { /* * If verstage_soc_early_init fails, cmos is probably not * accessible, so rebooting into recovery is not an option. @@ -266,33 +296,37 @@
post_code(POSTCODE_VERSTAGE_MAIN);
- vboot_run_logic(); + if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + vboot_run_logic();
- ctx = vboot_get_context(); - retval = check_cmos_recovery(); - if (retval) - reboot_into_recovery(ctx, retval);
- post_code(POSTCODE_UPDATE_BOOT_REGION); + ctx = vboot_get_context(); + retval = check_cmos_recovery(); + if (retval) + reboot_into_recovery(ctx, retval);
- /* - * Since psp_verstage doesn't load next stage we never call - * any cbfs API on RO path. However we still need to initialize - * RO CBFS MCACHE manually to pass it in transfer_buffer. - * In RW path, MCACHE build will be skipped for RO region since - * we already built here. - */ - cbfs_get_boot_device(true); + post_code(POSTCODE_UPDATE_BOOT_REGION);
- retval = update_boot_region(ctx); - if (retval) - reboot_into_recovery(ctx, retval); + /* + * Since psp_verstage doesn't load next stage we never call + * any cbfs API on RO path. However we still need to initialize + * RO CBFS MCACHE manually to pass it in transfer_buffer. + * In RW path, MCACHE build will be skipped for RO region since + * we already built here. + */ + cbfs_get_boot_device(true);
- post_code(POSTCODE_SAVE_BUFFERS); - retval = save_buffers(&ctx); - if (retval) - reboot_into_recovery(ctx, retval); + retval = update_boot_region(ctx); + if (retval) + reboot_into_recovery(ctx, retval);
+ post_code(POSTCODE_SAVE_BUFFERS); + retval = save_buffers(&ctx); + if (retval) + reboot_into_recovery(ctx, retval); + } else { + save_min_buffers(); + }
post_code(POSTCODE_UNMAP_SPI_ROM); boot_dev_base = rdev_mmap_full(boot_device_ro()); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 92607a3..cf1f569 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -118,8 +118,7 @@
config PSP_SHAREDMEM_BASE hex - default 0x2011000 if VBOOT - default 0x0 + default 0x2011000 help This variable defines the base address in DRAM memory where PSP copies the vboot workbuf. This is used in the linker script to have a static @@ -128,8 +127,7 @@
config PSP_SHAREDMEM_SIZE hex - default 0x8000 if VBOOT - default 0x0 + default 0x8000 help Sets the maximum size for the PSP to pass the vboot workbuf and any logs or timestamps back to coreboot. This will be copied @@ -428,8 +426,7 @@
config PSP_VERSTAGE_FILE string "Specify the PSP_verstage file path" - depends on VBOOT_STARTS_BEFORE_BOOTBLOCK - default "$(obj)/psp_verstage.bin" + default "./psp_verstage.bin" help Add psp_verstage file to the build & PSP Directory Table
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7db4719..6c4ec66 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -132,7 +132,7 @@ APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h)
-ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK)$(CONFIG_MIN_PSP_VERSTAGE),y) # type = 0x6B - PSP Shared memory location ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) @@ -142,8 +142,7 @@ # type = 0x52 - PSP Bootloader Userspace Application (verstage) PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK || CONFIG_MIN_PSP_VERSTAGE
# Helper function to return a value with given bit set # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.