[coreboot-gerrit] Change in ...coreboot[master]: src: Use CRx_TYPE type for cr

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33816

Change subject: src: Use CRx_TYPE type for cr
......................................................................

src: Use CRx_TYPE type for cr

Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/x86/lapic/lapic_cpu_init.c
M src/include/cpu/x86/cache.h
M src/northbridge/amd/amdmct/mct/mctdqs_d.c
M src/northbridge/amd/amdmct/mct/mctsrc.c
M src/northbridge/amd/amdmct/mct/mcttmrl.c
M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
M src/soc/intel/quark/reg_access.c
9 files changed, 16 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/33816/1

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 0f73e71..cbbc10d 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -417,7 +417,7 @@
     * Seems that CR4 was cleared when AP start via lapic_start_cpu()
     * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
     */
-	u32 cr4_val;
+	CRx_TYPE cr4_val;
    cr4_val = read_cr4();
    cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT);
    write_cr4(cr4_val);
diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index c8d26ab..7f135e5 100644
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -67,7 +67,7 @@
  */
 static __always_inline void enable_cache(void)
 {
-	unsigned long cr0;
+	CRx_TYPE cr0;
    cr0 = read_cr0();
    cr0 &= ~(CR0_CD | CR0_NW);
    write_cr0(cr0);
@@ -76,7 +76,7 @@
 static __always_inline void disable_cache(void)
 {
    /* Disable and write back the cache */
-	unsigned long cr0;
+	CRx_TYPE cr0;
    cr0 = read_cr0();
    cr0 |= CR0_CD;
    wbinvd();
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 36ee3ab..2e52a39 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -278,7 +278,7 @@
    u8 dqsWrDelay_end;

u32 addr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 649c1c8..406547e 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -129,7 +129,7 @@
    u32 index_reg;
    u32 ch_start, ch_end, ch;
    u32 msr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

u8 valid;
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index a78d42d..6ec4d64 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -122,7 +122,7 @@
    u32 PatternBuffer[60];	// FIXME: why not 48 + 4
    u32 Margin;
    u32 addr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

u8 valid;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 34b13ea..6b31294 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -16,6 +16,7 @@

#include <inttypes.h>
 #include <console/console.h>
+#include <cpu/x86/cr.h>
 #include <string.h>
 #include <arch/cpu.h>
 #include <cpu/amd/msr.h>
@@ -405,7 +406,7 @@
    u32 dev;
    u32 addr;
    u8 valid;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;
    u32 index_reg;
    uint32_t TestAddr;
@@ -1617,7 +1618,7 @@
    u8 _Wrap32Dis = 0, _SSE2 = 0;

u32 addr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

uint8_t dct;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index a6faf90..032152c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -22,6 +22,7 @@
 #include <arch/cpu.h>
 #include <inttypes.h>
 #include <console/console.h>
+#include <cpu/x86/cr.h>
 #include <string.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
@@ -612,7 +613,7 @@
    u32 index_reg;
    u32 ch_start, ch_end, ch;
    msr_t msr;
-	u32 cr4;
+	CRx_TYPE cr4;

uint32_t dword;
    uint8_t dimm;
@@ -1186,7 +1187,7 @@
    u32 index_reg;
    u32 ch_start, ch_end, ch;
    u32 msr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

uint32_t dword;
@@ -1583,7 +1584,7 @@
    u32 index_reg;
    u32 ch_start, ch_end;
    u32 msr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

uint32_t dword;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index e7b7883..ec9b8e4 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -21,7 +21,7 @@
 #include <inttypes.h>
 #include <console/console.h>
 #include <cpu/amd/msr.h>
-
+#include <cpu/x86/cr.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"

@@ -119,7 +119,7 @@
    u32 PatternBuffer[60];	/* FIXME: why not 48 + 4 */
    u32 Margin;
    u32 addr;
-	u32 cr4;
+	CRx_TYPE cr4;
    u32 lo, hi;

u8 valid;
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index 1063525..5e5acd8 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -18,6 +18,7 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/pci_ops.h>