[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add chip config for SATA strength

[Jamie Chen (Code Review)]

Hello Patrick Rudolph, Edward O'Callaghan, Tim Chen, Tim Wawrzynczak, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38432

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: Add chip config for SATA strength
......................................................................

soc/intel/cannonlake: Add chip config for SATA strength

Add config to chip.h for tuning SATA gen3 strength.

BUG=b:147351936
BRANCH=none
TEST=build successful in puff

Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e
Signed-off-by: Jamie Chen 
---
M src/soc/intel/cannonlake/chip.h
A src/soc/intel/cannonlake/include/soc/sata.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
3 files changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/38432/4