[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )

Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
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Patch Set 15: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... 
File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:

https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... 
PS13, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
             : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
             : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
             : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
> i'm curious - why 0xff here instead of 0x00?

You are right. Updated them to zeroes.