huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... PS2, Line 1608: 1792
@huayang, why is this 1792? The delta is more than other (8), also it's too different from original […]
the real clock DRAM control using is 796, 1596 and 1792 for avoid other RF device.
Dram Type= 6, Freq= 796, FreqGroup= 800, CH_0, rank 0 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 Dram Type= 6, Freq= 1792, FreqGroup= 1866, CH_0, rank 0