[coreboot-gerrit] Change in coreboot[master]: soc/baytrail: add ACPI method to generate USB port info

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19973 )

Change subject: soc/baytrail: add ACPI method to generate USB port info
......................................................................

soc/baytrail: add ACPI method to generate USB port info

Add ACPI method GPLD to generate port location data when
passed visiblity info.  Will be used by _PLD method in
board-specific USB .asl files.

Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718
Signed-off-by: Matt DeVillier 
---
M src/soc/intel/baytrail/acpi/xhci.asl
1 file changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/19973/1

diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl
index bef0b9f..339537c 100644
--- a/src/soc/intel/baytrail/acpi/xhci.asl
+++ b/src/soc/intel/baytrail/acpi/xhci.asl
@@ -23,6 +23,23 @@
    Device (RHUB)
    {
    	Name (_ADR, 0x00000000)
+
+		// GPLD: Generate Port Location Data (PLD)
+		Method (GPLD, 1, Serialized) {
+				Name (PCKG, Package (0x01) {
+					Buffer (0x10) {}
+				})
+
+				// REV: Revision 0x02 for ACPI 5.0
+				CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV)
+				Store (0x02, REV)
+
+				// VISI: Port visibility to user per port
+				CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI)
+				Store (Arg0, VISI)
+				Return (PCKG)
+		}
+
    	Device (PRT1) { Name (_ADR, 1) }
    	Device (PRT2) { Name (_ADR, 2) }
    	Device (PRT3) { Name (_ADR, 3) }