[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46856 )

Change subject: soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement
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soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement

Expose a config option that allows enabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port.

This UPD is enabled by default in FSP but interferes with achieving
deeper S0ix substates so in order to prevent it from needing to be
explicitly disabled for every root port this change makes disabling it
the default and allows it to be enabled if needed.

BUG=b:160996445
TEST=boot on volteer with PTM disabled by default for all root ports
and ensure S0i3.2 substate can be achieved.

Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46856
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 6a48ad0..5c124de 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -242,6 +242,9 @@
    /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
    uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];

+	/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */
+	uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 6de098a..ed34897 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -187,6 +187,7 @@
    	params->PcieRpAdvancedErrorReporting[i] =
    		config->PcieRpAdvancedErrorReporting[i];
    	params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+		params->PciePtm[i] = config->PciePtm[i];
    }

/* Enable ClkReqDetect for enabled port */