[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE

[Shuo Liu (Code Review)]

Attention is currently required from: Chen, Gang C.

Hello Chen, Gang C,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/84302?usp=email

to review the following change.

Change subject: soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE
......................................................................

soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE

For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.

Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen 
Signed-off-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/gnr/Kconfig
1 file changed, 0 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/84302/1

diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index 790f20e..fae9d8d 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -56,15 +56,6 @@
      and/or romstage. FSP-T reserves the upper 0x100 for
      FspReservedBuffer.

-config DCACHE_BSP_STACK_SIZE
-	hex
-	default 0x60000
-	help
-	  The amount of anticipated stack usage in CAR by bootblock and
-	  other stages. It needs to include FSP-M stack requirement and
-	  CB romstage stack requirement. The integration documentation
-	  says this needs to be 256KiB.
-
 config FSP_M_RC_HEAP_SIZE
    hex
    default 0x142000