[coreboot-gerrit] New patch to review for coreboot: ea7088a AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in Yangtze

[Siyuan Wang]

Siyuan Wang ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3879

-gerrit

commit ea7088a598604043c1bb3a1a8ee1adfe89b44610
Author: WANG Siyuan 
Date:   Wed Aug 21 10:06:25 2013 +0800

AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in Yangtze

src/southbridge/amd/agesa/hudson/Kconfig config default value,
    mainboard Kconfig config value for specific mainboard.
    bit 1,0 - pin 0
    bit 3,2 - pin 1
    bit 5,4 - pin 2
    bit 7,6 - pin 3

Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
    Signed-off-by: WANG Siyuan 
    Signed-off-by: WANG Siyuan 
---
 src/southbridge/amd/agesa/hudson/Kconfig                         | 9 +++++++++
 .../f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c      | 8 ++++----
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 5cb1722..7e7399c 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -247,4 +247,13 @@ if SOUTHBRIDGE_AMD_AGESA_YANGTZE
    config AMD_SB_SPI_TX_LEN
    	int
    	default 64
+
+	config AZ_PIN
+		hex
+		default 0xaa
+		help
+		  bit 1,0 - pin 0
+		  bit 3,2 - pin 1
+		  bit 5,4 - pin 2
+		  bit 7,6 - pin 3
 endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
index 888b83c..843bf82 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
@@ -266,10 +266,10 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
     0,                       // AzaliaSnoop
     0,                       // AzaliaDummy
     {                        // AZALIA_PIN
-      2,                     // AzaliaSdin0
-      2,                     // AzaliaSdin1
-      2,                     // AzaliaSdin2
-      2,                     // AzaliaSdin3
+      CONFIG_AZ_PIN & 0x3,                     // AzaliaSdin0
+      (CONFIG_AZ_PIN & 0xc) >> 2,                     // AzaliaSdin1
+      (CONFIG_AZ_PIN & 0x30) >> 4,                     // AzaliaSdin2
+      (CONFIG_AZ_PIN & 0xc0) >> 6,                     // AzaliaSdin3
     },
     NULL,                    // *AzaliaOemCodecTablePtr
     NULL,                    // *AzaliaOemFpCodecTablePtr