Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47879 )
Change subject: soc/intel/jasperlake: Fill software noise mitigation related UPDs ......................................................................
soc/intel/jasperlake: Fill software noise mitigation related UPDs
Purpose of this patch is to expose and fill software noise mitigation related parameters from coreboot so that we can fine tune noise mitigation
This is work in progress patch and final patchset will allow values to be filled from devietree once values are finalized
BUG=NONE BRANCH=NONE TEST=code compiles and UPDs are updated
Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47879/1
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 92c35c6..a76bea3 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -236,6 +236,25 @@ config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, config->PchPmPwrCycDur);
+ /* Disable Fast slew rate for Deeper C states */ + /* Note that each index is for specific VR */ + params->FastPkgCRampDisable[0] = 0x00; + params->FastPkgCRampDisable[1] = 0x00; + params->FastPkgCRampDisable[2] = 0x00; + params->FastPkgCRampDisable[3] = 0x00; + params->FastPkgCRampDisable[4] = 0x00; + + params->SlowSlewRate[0] = 0x00; + params->SlowSlewRate[1] = 0x00; + params->SlowSlewRate[2] = 0x00; + params->SlowSlewRate[3] = 0x00; + params->SlowSlewRate[4] = 0x00; + + params->AcousticNoiseMitigation = 0x00; + params->PreWake = 0x00; + params->RampUp = 0x00; + params->RampDown = 0x00; + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); }