[coreboot-gerrit] Change in coreboot[master]: soc/intel: Fix regression with hidden PCI devices

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34285 )

Change subject: soc/intel: Fix regression with hidden PCI devices
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Patch Set 5:
> Patch Set 4: 
> Huh.. so  you can write but cannot read? Or did you mean "unaffected -> not decoded" ?

That is my understanding i.e. you can write but cannot read.
> > What purpose would this "PCI_QUIRK_SPECS_VIOLATION" be used for?
>
> I would guard pcidev_path_on_root_debug() and/or dev_find_slot() behind this. So seeing that in the platform Kconfig would serve as a reminder that some ugly hack is in place and needs attention. We can call it DEBUG_PCI_TREE but I would like to select it for affected soc/intel.

Humm okay.. I think most recent Intel platforms behave this way i.e. P2SB gets hidden.