Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35026 )
Change subject: soc/intel/{cnl, icl}: Cache the TSEG region ......................................................................
Patch Set 7: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/35026/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35026/7//COMMIT_MSG@10 PS7, Line 10: normal boot and s3 resume on CML-hatch. 929 - 910 would be 19ms. I expect some variance here though.
https://review.coreboot.org/c/coreboot/+/35026/7//COMMIT_MSG@19 PS7, Line 19: Total Time: 910ms Aug 23 15:05 Total Time till picking kernel: 818,078
I cannot really determine from the comments if there was some major rebase of vboot or if the numbers even come from the same reference board. I'd like confirmation it was not a regression from some of the work done on common intel romstage, stack guards, or FSP heap/stack changes.
Once merged, performance data (cbmem -t) of this (and the parent) commit should be available for download somewhere. Those will become the reference when we evaluate if POSTCAR_STAGE=n makes any sense. If timestamp 1100 is now (mysteriously) fixed, POSTCAR_STAGE=n approaches are a regression for boot speed.