Attention is currently required from: Chen, Gang C, Ziang Wang.
Hello Chen, Gang C, Ziang Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/81439?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA ......................................................................
soc/intel/xeon_sp: Add SOC_INTEL_HAS_NUMA
NUMA and CXL supports are two different but correlated concepts. Add new Kconfig option to handle them separately. When SOC_INTEL_HAS_CXL selected, SOC_INTEL_HAS_NUMA will be selected.
Change-Id: I84f07c16e24e441a885144df8c805f1310acae29 Signed-off-by: Shuo Liu shuo.liu@intel.com Signed-off-by: Ziang Wang ziang.wang@intel.com Signed-off-by: Gang Chen gang.c.chen@intel.com --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/gnr/Kconfig M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/uncore_acpi.c 10 files changed, 39 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/81439/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 281d45a..17fd956 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -113,7 +113,11 @@ config HAVE_IOAT_DOMAINS bool
+config SOC_INTEL_HAS_NUMA + bool + config SOC_INTEL_HAS_CXL + select SOC_INTEL_HAS_NUMA bool
endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index eb39182..e0f96cd 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -14,7 +14,8 @@ ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c -ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c +ramstage-$(CONFIG_SOC_INTEL_HAS_NUMA) += numa.c +ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += smihandler.c pmutil.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 51e545f..c638801 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -9,6 +9,7 @@ select HAVE_INTEL_FSP_REPO select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING + select SOC_INTEL_HAS_NUMA help Intel Cooper Lake-SP support
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 2d6005b..3472d58 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -136,3 +136,8 @@ { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig index 1945be7..481a47a 100644 --- a/src/soc/intel/xeon_sp/gnr/Kconfig +++ b/src/soc/intel/xeon_sp/gnr/Kconfig @@ -17,6 +17,7 @@ select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select VPD select OCP_VPD + select SOC_INTEL_HAS_CXL help Intel GraniteRapids support
diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 62657dc..0186865 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -50,7 +50,6 @@
/* Fill in processor domains */ uint8_t i, j, socket; - struct device *dev; for (socket = 0, i = 0; i < num_sockets; socket++) { if (!soc_cpu_is_enabled(socket)) continue; @@ -73,6 +72,7 @@ if (num_cxlnodes == 0) return;
+#if CONFIG(SOC_INTEL_HAS_CXL) /* There are CXL nodes, fill in generic initiator domain after the processors pds */ uint8_t skt_id, cxl_id; const CXL_NODE_SOCKET *cxl_hob = get_cxl_node(); @@ -83,7 +83,7 @@ pds.pds[i].socket_bitmap = node.SocketBitmap; pds.pds[i].base = node.Address; pds.pds[i].size = node.Size; - dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); + struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); pds.pds[i].dev = dev; pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) @@ -97,6 +97,7 @@ } } } +#endif }
/* diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 4a9e683..462e59f 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,7 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select SOC_INTEL_HAS_NUMA help Intel Skylake-SP support
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 38d834f..5167a70 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -210,3 +210,8 @@ { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1d6d955..9a60805 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -281,7 +281,7 @@ { int index = 0;
- if (CONFIG(SOC_INTEL_HAS_CXL)) { + if (CONFIG(SOC_INTEL_HAS_NUMA)) { static bool once; if (!once) { /* Construct NUMA data structure. This is needed for CXL. */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index c88707e..17c25a5 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -574,21 +574,23 @@
const config_t *const config = config_of(device);
- /* SRAT */ - current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *)current; - acpi_create_srat(srat, acpi_fill_srat); - current += srat->header.length; - acpi_add_table(rsdp, srat); + if (CONFIG(SOC_INTEL_HAS_NUMA)) { + /* SRAT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *)current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat);
- /* SLIT */ - current = ALIGN_UP(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *)current; - acpi_create_slit(slit, acpi_fill_slit); - current += slit->header.length; - acpi_add_table(rsdp, slit); + /* SLIT */ + current = ALIGN_UP(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *)current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + }
if (CONFIG(SOC_INTEL_HAS_CXL)) { /* HMAT*/