Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 )
Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69680/comment/756a0aba_c1a6b5ea PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP.
I don't have access to crosbug:200644229. […]
Thanks for commit update and pushing the CL. I'm wondering how this CL applicable to MTL a
https://review.coreboot.org/c/coreboot/+/69680/comment/a915aa0a_68f05bf0 PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP.
I don't have access to crosbug:200644229. […]
Thanks for update. Considering the Arch change from ADL to MTL, the reported issue on ADL may not be applicable to MTL. We need to relook at the issue again on MTL.
Commit Message:
https://review.coreboot.org/c/coreboot/+/69680/comment/797d2206_3fa2a0b0 PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. Thanks for commit update. Since architectural change from ADL to MTL, I'm not sure if this is applicable to MTL.