Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39491 )
Change subject: soc/intel/cannonlake/bootblock: Fix FSP CAR ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39491/1/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/39491/1/src/soc/intel/cannonlake/bo... PS1, Line 32: #if CONFIG_ROM_SIZE > 16 * 1024 * 1024 : #define CODE_CACHE_SIZE (16 * 1024 * 1024) : #else : #define CODE_CACHE_SIZE CONFIG_ROM_SIZE : #endif
if run-time determination doesn't work, shall this not be defined by motherboard?
it could be defined by motherboard, but I don't see any issues marking the 16MiB as cached even if less are memory mapped. For simplicity let's stick with CODE_CACHE_SIZE.