Duan huayang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40525 )
Change subject: soc/mediatek/mt8183: Use term settings for high DRAM frequency ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40525/3/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_init_setting.c:
https://review.coreboot.org/c/coreboot/+/40525/3/src/soc/mediatek/mt8183/dra... PS3, Line 1222: SELPH_DQS0_3200
Hi huayang, I think this we still not answered yet?
we just use SELPH_DQS0_3200 for default value in dramc_setting() but for other frequency, for example 3600Mbps, it will overwrite this value like this. this flow is same as the DRAM full k blob that be verified.
static void dramc_setting_DDR3600(void) { clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } static void dramc_setting_DDR2400(void) { clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); }
dramc_setting() {
clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200); clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200);
switch (freq_group) { case LP4X_DDR1600: dramc_setting_DDR1600(); break; case LP4X_DDR2400: dramc_setting_DDR2400(); break; case LP4X_DDR3200: /* Do nothing */ break; case LP4X_DDR3600: dramc_setting_DDR3600(); break; default: die("Invalid DDR frequency group %u\n", freq_group); return; } }