[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Configure voltage margining policies

[Krzysztof M Sywula (Code Review)]

Krzysztof M Sywula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32026 )

Change subject: soc/intel/cannonlake: Configure voltage margining policies
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Patch Set 3:

(2 comments)

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 168: SlpS0WithGbeSupport
> Could this be set based on s0ix_enable+PchLanEnable? […]

"Could this be set based on s0ix_enable+PchLanEnable?" - yes, done
"The default seems to be enabled except on WHL V0, do we need to account for that in here as well to not try and force it on with WHL V0?" - no, as per documentation, SlpS0WithGbeSupport should be TRUE (1) for GbE enabled platforms, W0 and V0 steppings.

https://review.coreboot.org/#/c/32026/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 169: PchPmSlpS0VmRuntimeControl
> I became aware of a documentation that specifies how these parameters should be configured for GbE s […]

Done