Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30655
Change subject: util/autoport/readme.md: Correct minor inconsistency ......................................................................
util/autoport/readme.md: Correct minor inconsistency
CB:28851 changed where the SPD map is. Reflect that.
Change-Id: Id0bd1778617371bac5921c4eae63d0beb088216c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M util/autoport/readme.md 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30655/1
diff --git a/util/autoport/readme.md b/util/autoport/readme.md index 67a2c56..226fcda 100644 --- a/util/autoport/readme.md +++ b/util/autoport/readme.md @@ -80,7 +80,7 @@ most likely correct. In order to initialize the memory coreboot needs to know RAM timings. For socketed RAM it's stored in a small EEPROM chip which can be accessed through SPD. Unfortunately mapping between SPD addresses and RAM slots differs and cannot always be detected automatically. -Resulting SPD map is encoded in function `mainboard_get_spd` in `early_southbridge.c`. +Resulting SPD map is encoded in function `mainboard_get_spd` in `romstage.c`. autoport uses the most common map `0x50, 0x51, 0x52, 0x53` except for lenovos which are known to use `0x50, 0x52, 0x51, 0x53`. To detect the correct memory map the easiest way is with vendor BIOS to boot with just one module in channel 0 slot 0 and then see where does it show