Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45391 )
Change subject: drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region ......................................................................
Patch Set 1:
(6 comments)
Thanks for the feedbacks!
https://review.coreboot.org/c/coreboot/+/45391/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45391/1//COMMIT_MSG@7 PS1, Line 7: ask
Use
Done
https://review.coreboot.org/c/coreboot/+/45391/1//COMMIT_MSG@20 PS1, Line 20:
I am confused by this commit message. […]
Done
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/cb... File src/drivers/intel/fsp2_0/cbmem.c:
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/cb... PS1, Line 9: void *tolum_base;
Let's avoid void * arithmetic if we can. […]
Done
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/cb... PS1, Line 14: return tolum_base + cbmem_overhead_size();
Please add a comment why range_entry_end() cannot be used.
Done
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/cb... PS1, Line 15: }
It doesn't seem like cbmem_top_chipset() should change. […]
In order to support RAS, a new type of memory region needs to be added. Such memory region holds data such as boot time error record and run time error record. The memory region needs to be accessible by both firmware and OS, but reserved from regular OS usage. CBMEM cannot be used for this, as CBMEM is added as type 16 as "configuration table". OS (bert and hest) drivers can not access data in CBMEM. Hence we reserve this memory region together with CBMEM meta data through FSP. CBMEM metadata has to bee next to the rest of CBMEM data, so this (BERT) memory region needs to be on top of CBMEM region. In this memory map arrangement, bert_base is the same as cbmem_top.
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/ho... File src/drivers/intel/fsp2_0/hob_verify.c:
https://review.coreboot.org/c/coreboot/+/45391/1/src/drivers/intel/fsp2_0/ho... PS1, Line 47: printk(BIOS_DEBUG, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
It seems that this should do the correct check for tolum, cbmem_top, and bert.
Done